Senior Digital Design Engineer

22 hours ago

Brno, South Moravian, Czech Republic onsemi Full time 1,200,000 - 2,400,000 per year
Description

About the Role

At onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world's most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Join onsemi's New Product Development team in Brno, Czech Republic, where we define, design, and validate cutting-edge analog-digital integrated circuits.

We are looking for an Experienced Digital Design Engineer to join our team on our journey to defining and developing the next generation of innovative driver devices and solutions.

Responsibilities

What You'll Do

  • Design and verify digital circuits using HDL languages.
  • Work on digital design architecture implementation using Verilog, system Verilog.
  • Perform synthesis and design-for-test (DFT) implementation.
  • Collaborate on block integration in complex mixed-signal designs.
  • Implement Digital On Top (DOT) for SoC design using sub-system IPs and analog IPs.
  • Contribute to design documentation and test plans.
  • Collaborate on block integration in complex mixed-signal designs.
  • Work with cross functional team for verification and physical design.
  • Ensure first-pass success and timely execution using established design methodologies.
Qualifications

What We're Looking For

  • MS or BS in Electrical Engineering, Computer Science, or a related field.
  • 3+ years of professional experience in digital design. 
  • Experience in HDL languages – Verilog, SystemVerilog, or VHDL.
  • Knowledge of functional verification concepts, especially UVM.
  • Good understanding of digital design principles.
  • Strong motivation to learn and grow in technical expertise.
  • Good communication skills in English (written and spoken).
  • Eligibility to work in the Czech Republic.

Preferred Skills

  • Experience in SoC design flow – RTL design, simulation, verification DFT, signoff.
  • Experience with SystemVerilog behavioral modeling.

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